Model Synthesis for Communication Traces of System-on-Chip Designs

TL;DR

This paper presents a method to automatically infer system-level communication models for SoC designs from communication traces using SMT solvers, aiding design analysis and validation.

Contribution

It formulates the model inference problem as a constraint satisfaction problem solved by SMT solvers, enabling automated extraction of communication protocols from traces.

Findings

Successfully inferred models from real SoC communication traces

Demonstrated approach on both transaction-level and detailed GEM5 simulation traces

Effective in capturing system-level communication behaviors

Abstract

Concise and abstract models of system-level behaviors are invaluable in design analysis, testing, and validation. In this paper, we consider the problem of inferring models from communication traces of system-on-chip~(SoC) designs. The traces capture communications among different blocks of a SoC design in terms of messages exchanged. The extracted models characterize the system-level communication protocols governing how blocks exchange messages, and coordinate with each other to realize various system functions. In this paper, the above problem is formulated as a constraint satisfaction problem, which is then fed to a SMT solver. The solutions returned by the SMT solver are used to extract the models that accept the input traces. In the experiments, we demonstrate the proposed approach with traces collected from a transaction-level simulation model of a multicore SoC design and traces of a more detailed multicore SoC design developed in GEM5 environment.