Transparent FPGA Acceleration with TensorFlow

TL;DR

This paper presents a flexible FPGA acceleration framework integrated with TensorFlow, enabling dynamic reconfiguration and simplified development for neural network workloads without requiring specialized toolchains.

Contribution

It introduces an HSA-based toolflow that allows FPGA hardware to be dynamically reconfigured during runtime, simplifying neural network acceleration development.

Findings

Supports dynamic FPGA reconfiguration during neural network execution

Provides a familiar TensorFlow frontend for developers

Enables hardware flexibility and runtime adaptability

Abstract

Today, artificial neural networks are one of the major innovators pushing the progress of machine learning. This has particularly affected the development of neural network accelerating hardware. However, since most of these architectures require specialized toolchains, there is a certain amount of additional effort for developers each time they want to make use of a new deep learning accelerator. Furthermore the flexibility of the device is bound to the architecture itself, as well as to the functionality of the runtime environment. In this paper we propose a toolflow using TensorFlow as frontend, thus offering developers the opportunity of using a familiar environment. On the backend we use an FPGA, which is addressable via an HSA runtime environment. In this way we are able to hide the complexity of controlling new hardware from the user, while at the same time maintaining a high amount of flexibility. This can be achieved by our HSA toolflow, since the hardware is not statically configured with the structure of the network. Instead, it can be dynamically reconfigured during runtime with the respective kernels executed by the network and simultaneously from other sources e.g. OpenCL/OpenMP.