Contact-Barrier Free, High Mobility, Dual-Gated Junctionless Transistor Using Tellurium Nanowire
Pushkar Dasika, Debadarshini Samantaray, Krishna Murali, Nithin, Abraham, Kenji Watanabe, Takashi Taniguchi, N. Ravishankar, and Kausik, Majumdar

TL;DR
This paper demonstrates a dual-gated junctionless tellurium nanowire transistor with high mobility and low contact resistance, promising for next-generation sub-5 nm electronic devices.
Contribution
It introduces a novel tellurium nanowire junctionless transistor with high mobility and zero Schottky barrier, advancing scalable, high-performance nanoelectronics.
Findings
Achieved a phonon-limited hole mobility of 570 cm²/V·s at 270 K.
Mobility increases to 1390 cm²/V·s at lower temperatures.
Realized a high drive current of 216 μA/μm with an on-off ratio over 2×10^4.
Abstract
Gate-all-around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub-5 nm technology node. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here we demonstrate a dual-gated junctionless nanowire \emph{p}-type field effect transistor using tellurium nanowire as the channel. The dangling-bond-free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling-bond-free, high quality hBN gate dielectric, allows us to achieve a phonon-limited field effect hole mobility of at 270 K, which is well above state-of-the-art strained Si hole mobility. By lowering the temperature, the mobility increases…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
