Fuzzing Hardware Like Software
Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly,, Dominic Rizzo, Matthew Hicks

TL;DR
This paper proposes adapting software fuzzing techniques to hardware verification by translating RTL hardware into software models, enabling more efficient detection of subtle hardware flaws and achieving significant coverage improvements.
Contribution
It introduces a novel approach of using software fuzzers for hardware design verification by translating RTL to software models and addressing key challenges in test case representation and coverage.
Findings
Two orders-of-magnitude reduction in verification runtime
Over 88% HDL line coverage achieved in most designs
Effective detection of subtle hardware flaws
Abstract
Hardware flaws are permanent and potent: hardware cannot be patched once fabricated, and any flaws may undermine any software executing on top. Consequently, verification time dominates implementation time. The gold standard in hardware Design Verification (DV) is concentrated at two extremes: random dynamic verification and formal verification. Both struggle to root out the subtle flaws in complex hardware that often manifest as security vulnerabilities. The root problem with random verification is its undirected nature, making it inefficient, while formal verification is constrained by the state-space explosion problem, making it infeasible against complex designs. What is needed is a solution that is directed, yet under-constrained. Instead of making incremental improvements to existing DV approaches, we leverage the observation that existing software fuzzers already provide such a…
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Taxonomy
TopicsSoftware Testing and Debugging Techniques · Advanced Malware Detection Techniques · Embedded Systems Design Techniques
