Understanding Cache Boundness of ML Operators on ARM Processors

TL;DR

This paper analyzes the cache-boundness of ML operators on ARM processors, revealing that GEMM and convolutions are limited by cache bandwidth, and quantization can improve speed but depends on data layout.

Contribution

It provides the first detailed analysis of ML operators' cache behavior on ARM, comparing hardware limits with actual performance, and explores quantization effects.

Findings

GEMM and convolutions are cache bandwidth bound on ARM.

Quantization can significantly speed up operators.

Performance depends on data layout and bit packing interactions.

Abstract

Machine Learning compilers like TVM allow a fast and flexible deployment on embedded CPUs. This enables the use of non-standard operators, which are common in ML compression techniques. However, it is necessary to understand the limitations of typical compute-intense operators in ML workloads to design a proper solution. This is the first in-detail analysis of dense and convolution operators, generated with TVM, that compares to the fundamental hardware limits of embedded ARM processors. Thereby it explains the gap between computational peak performance, theoretical and measured, and real-world state-of-the-art results, created with TVM and openBLAS. Instead, one can see that single-precision general matrix multiply (GEMM) and convolutions are bound by L1-cache-read bandwidth. Explorations of 8-bit and bit-serial quantized operators show that quantization can be used to achieve relevant speedups compared to cache-bound floating-point operators. However, the performance of quantized operators highly depends on the interaction between data layout and bit packing.