Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir Computing

TL;DR

This paper introduces a direct spatial FPGA implementation of sparse matrix multipliers for reservoir computing, significantly reducing latency and power consumption compared to GPU and DNN accelerators, with potential for ASIC deployment.

Contribution

It presents a novel bit-serial, spatial FPGA architecture for sparse matrix multiplication that outperforms existing GPU and DNN accelerators in latency and efficiency.

Findings

FPGA implementation reduces latency by up to 86x compared to GPU libraries.

Achieves 4.1x to 47x latency reduction over recent sparse DNN accelerators.

Throughput remains competitive across various matrix sizes and batch configurations.

Abstract

Reservoir computing systems rely on the recurrent multiplication of a very large, sparse, fixed matrix. We argue that direct spatial implementation of these fixed matrices minimizes the work performed in the computation, and allows for significant reduction in latency and power through constant propagation and logic minimization. Bit-serial arithmetic enables massive static matrices to be implemented. We present the structure of our bit-serial matrix multiplier, and evaluate using canonical signed digit representation to further reduce logic utilization. We have implemented these matrices on a large FPGA and provide a cost model that is simple and extensible. These FPGA implementations, on average, reduce latency by 50x up to 86x versus GPU libraries. Comparing against a recent sparse DNN accelerator, we measure a 4.1x to 47x reduction in latency depending on matrix dimension and sparsity. Throughput of the FPGA solution is also competitive for a wide range of matrix dimensions and batch sizes. Finally, we discuss ways these techniques could be deployed in ASICs, making them applicable for dynamic sparse matrix computations.