Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications

TL;DR

This paper demonstrates the automatic synthesis of a space shooter game on FPGA using Temporal Stream Logic, showcasing the potential of TSL for scalable hardware design from high-level specifications.

Contribution

It introduces Syntroids, a novel FPGA game synthesized entirely from TSL specifications, highlighting the advantages of TSL in hardware synthesis.

Findings

Syntroids was successfully implemented on FPGA using TSL.

Synthesis quality compares favorably to manual programming.

Discussion of current challenges in TSL-based synthesis tools.

Abstract

We present Syntroids, a case study for the automatic synthesis of hardware from a temporal logic specification. Syntroids is a space shooter arcade game realized on an FPGA, where the control flow architecture has been completely specified in Temporal Stream Logic (TSL) and implemented using reactive synthesis. TSL is a recently introduced temporal logic that separates control and data. This leads to scalable synthesis, because the cost of the synthesis process is independent of the complexity of the handled data. In this case study, we report on our experience with the TSL-based development of the Syntroids game and on the implementation quality obtained with synthesis in comparison to manual programming. We also discuss solved and open challenges with respect to currently available synthesis tools.