Non-volatile reconfigurable spin logic device: parallel operations

TL;DR

This paper proposes a non-volatile, reprogrammable spin logic device capable of parallel Boolean operations, demonstrating improved performance and reduced power consumption compared to conventional logic families, with potential for nano-scale circuit design.

Contribution

Introduces a novel spin-based logic device that performs multiple Boolean operations in parallel, enhancing efficiency and reconfigurability over existing technologies.

Findings

Device performs multiple logic operations simultaneously.

Parallel operations outperform conventional logic families.

Reduced power consumption and wiring complexity.

Abstract

A new proposal is given for designing a non-volatile, completely spin logic device, that can be reprogrammed for different functional classical logical operations. We use the concept of bias driven spin dependent circular current and current induced magnetic field in a quantum ring under asymmetric ring-to-electrode interface configuration to implement all the Boolean operations. We extend our idea to build two kinds of parallel computing architectures for getting parallelized operations, all at a particular time. For one case, different kinds of parallel operations are performed in a single device, whereas in the other type all the possible inputs of a logic gate are processed in parallel and all the outputs are read simultaneously. The performance and reliability are investigated in terms of power, delay and power-delay-product and finally the system temperature. We find that both the individual and simultaneous logic operations studied here are much superior compared to the operations performed in different conventional logic families like complementary metal oxide semiconductor logic, transistor-transistor logic, etc. The key advantage is that we can perform several logic operations, as many as we wish, repeating the same or different logic gates using a single setup, which indeed reduces wiring in the circuits and hence consumes much less power. Our analysis can be utilized to design optimized logic circuits at nano-scale level.