Robust and Attack Resilient Logic Locking with a High Application-Level Impact
Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, Ankur Srivastava

TL;DR
This paper introduces Strong Anti-SAT (SAS) and Robust SAS (RSAS), novel logic locking schemes that achieve high security against SAT and removal attacks while maintaining high application-level impact, surpassing existing methods.
Contribution
The paper presents SAS and RSAS, new logic locking techniques that break the traditional trade-off between SAT resilience and effectiveness, and demonstrates their high security and application-level impact.
Findings
SAS and RSAS resist SAT and removal attacks effectively.
SAS and RSAS outperform SFLL in SAT resilience.
SAS has high application-level impact when integrated into processors.
Abstract
Logic locking is a hardware security technique to intellectual property (IP) against security threats in the IC supply chain, especially untrusted fabs. Such techniques incorporate additional locking circuitry within an IC that induces incorrect functionality when an incorrect key is provided. The amount of error induced is known as the effectiveness of the locking technique. "SAT attacks" provide a strong mathematical formulation to find the correct key of locked circuits. In order to achieve high SAT resilience(i.e. complexity of SAT attacks), many conventional logic locking schemes fail to inject sufficient error into the circuit. For example, in the case of SARLock and Anti-SAT, there are usually very few (or only one) input minterms that cause any error at the circuit output. The state-of-the-art stripped functionality logic locking (SFLL) technique introduced a trade-off between…
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Taxonomy
TopicsPhysical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis · Neuroscience and Neural Engineering
