
TL;DR
This paper compares ternary and binary adder implementations, showing that ternary adders using MUX are more transistor-efficient than binary counterparts, with a consistent ratio exceeding the theoretical information ratio.
Contribution
It introduces efficient ternary adder designs using MUX and compares their transistor count with binary implementations, highlighting superior efficiency.
Findings
Ternary adders with MUX have lower transistor counts than binary versions.
Transistor count ratio exceeds the theoretical information ratio.
Ternary implementations are more transistor-efficient overall.
Abstract
The MUX implementation of ternary half adders and full adders using predecessor and successor functions lead to the most efficient efficient implementation using the smallest transistor count. These designs are compared with the binary implementation of the corresponding half adders and full adders using the MUX technique or the typical complementary CMOS circuit style. The transistor count ratio between ternary and binary implementations is always greater than the information ratio ( = 1.585) between ternary and binary wires.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsLow-power high-performance VLSI design · VLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing
