TSV-integrated Surface Electrode Ion Trap for Scalable Quantum Information Processing

TL;DR

This paper introduces a novel TSV-integrated ion trap that significantly reduces size and parasitic capacitance, demonstrating compatibility with CMOS processes and effective ion trapping for scalable quantum computing.

Contribution

First demonstration of Cu-filled TSVs integrated into an ion trap, enabling scalable design with reduced form factor and maintained ion trapping performance.

Findings

80% reduction in trap size

Parasitic capacitance decreased from 32 to 3 pF

Ion lifetime of ~30 minutes with low heating rate

Abstract

In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.