Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing
Sairam Sri Vatsavai, Ishan Thakkar

TL;DR
This paper introduces a silicon photonic microring based chip-scale delayed feedback reservoir computing accelerator that significantly improves energy efficiency, accuracy, and training speed over previous photonic and electronic implementations.
Contribution
It presents a novel MR-based nonlinear neuron and on-chip photonic delay loop, achieving better accuracy and faster training than prior photonic and electronic DFRC accelerators.
Findings
35% lower NRMSE for NARMA10 prediction
98.7% lower NRMSE for Santa Fe time series
58.8% lower SER for channel equalization
Abstract
To perform temporal and sequential machine learning tasks, the use of conventional Recurrent Neural Networks (RNNs) has been dwindling due to the training complexities of RNNs. To this end, accelerators for delayed feedback reservoir computing (DFRC) have attracted attention in lieu of RNNs, due to their simple hardware implementations. A typical implementation of a DFRC accelerator consists of a delay loop and a single nonlinear neuron, together acting as multiple virtual nodes for computing. In prior work, photonic DFRC accelerators have shown an undisputed advantage of fast computation over their electronic counterparts. In this paper, we propose a more energy-efficient chip-scale DFRC accelerator that employs a silicon photonic microring (MR) based nonlinear neuron along with on-chip photonic waveguides-based delayed feedback loop. Our evaluations show that, compared to a well-known…
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