Quantitative Evaluation of Hardware Binary Stochastic Neurons
Orchi Hassan, Supriyo Datta, and Kerem Y. Camsari

TL;DR
This paper evaluates the design and performance of hardware binary stochastic neurons (BSNs) for Ising Machines, focusing on their scalability, energy efficiency, and device-level conditions for optimal operation.
Contribution
It extends previous work by classifying conditions for designing fast, energy-efficient BSNs and connects device analysis to system-level performance metrics.
Findings
Identifies necessary and sufficient conditions for BSN design.
Proposes hardware-independent metrics like flips per second and energy per bit.
Highlights the potential for scalable, low-footprint Ising Machine implementations.
Abstract
Recently there has been increasing activity to build dedicated Ising Machines to accelerate the solution of combinatorial optimization problems by expressing these problems as a ground-state search of the Ising model. A common theme of such Ising Machines is to tailor the physics of underlying hardware to the mathematics of the Ising model to improve some aspect of performance that is measured in speed to solution, energy consumption per solution or area footprint of the adopted hardware. One such approach to build an Ising spin, or a binary stochastic neuron (BSN), is a compact mixed-signal unit based on a low-barrier nanomagnet based design that uses a single magnetic tunnel junction (MTJ) and three transistors (3T-1MTJ) where the MTJ functions as a stochastic resistor (1SR). Such a compact unit can drastically reduce the area footprint of BSNs while promising massive scalability by…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
