Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems

TL;DR

This paper investigates how critical data delays in NoC-based inter-core communication impact multi-threaded application performance and demonstrates that NoC-aware memory optimizations can significantly reduce latency and improve system throughput.

Contribution

It provides insights into critical data request behavior and proposes NoC-aware memory access optimizations to enhance performance in many-core systems.

Findings

Critical data delay causes 60-75% of miss latency.

NoC-aware optimizations reduce miss penalty by 10-12%.

System performance improves by 7-11%.

Abstract

Multi-threaded applications are capable of exploiting the full potential of many-core systems. However, Network-on-Chip (NoC) based inter-core communication in many-core systems is responsible for 60-75% of the miss latency experienced by multi-threaded applications. Delay in the arrival of critical data at the requesting core severely hampers performance. This brief presents some interesting insights about how critical data is requested from the memory by multi-threaded applications. Then it investigates the cause of delay in NoC and how it affects the performance. Finally, this brief shows how NoC-aware memory access optimisations can significantly improve performance. Our experimental evaluation considers early restart memory access optimisation and demonstrates that by exploiting NoC resources, critical data can be prioritised to reduce miss penalty by 10-12% and improve system performance by 7-11%.