Learning algorithms from circuit lower bounds

TL;DR

This paper establishes a deep connection between circuit lower bounds and learning algorithms, showing that efficient error-finding in circuits implies PAC learning with small circuits, extending the natural proofs barrier.

Contribution

It provides a new characterization of learning algorithms based on circuit lower bounds and introduces a novel proof technique using Nisan-Wigderson generators.

Findings

Efficient error-finding in circuits implies PAC learnability with small circuits.

The opposite direction also holds, linking circuit lower bounds and learning.

An alternative proof of learning speedup from circuit lower bounds is presented.

Abstract

We revisit known constructions of efficient learning algorithms from various notions of constructive circuit lower bounds such as distinguishers breaking pseudorandom generators or efficient witnessing algorithms which find errors of small circuits attempting to compute hard functions. As our main result we prove that if it is possible to find efficiently, in a particular interactive way, errors of many p-size circuits attempting to solve hard problems, then p-size circuits can be PAC learned over the uniform distribution with membership queries by circuits of subexponential size. The opposite implication holds as well. This provides a new characterisation of learning algorithms and extends the natural proofs barrier of Razborov and Rudich. The proof is based on a method of exploiting Nisan-Wigderson generators introduced by Kraj\'{i}\v{c}ek (2010) and used to analyze complexity of circuit lower bounds in bounded arithmetic. An interesting consequence of known constructions of learning algorithms from circuit lower bounds is a learning speedup of Oliveira and Santhanam (2016). We present an alternative proof of this phenomenon and discuss its potential to advance the program of hardness magnification.