Fundamental Limits on Energy-Delay-Accuracy of In-memory Architectures in Inference Applications

TL;DR

This paper establishes fundamental limits on the precision, energy, and delay of in-memory computing architectures (IMCs) for inference, analyzing noise models and SNR metrics to optimize accuracy and efficiency.

Contribution

It introduces a noise model and SNR analysis framework for IMCs, proposes the minimum precision criterion (MPC), and compares three compute models to optimize energy-delay-accuracy trade-offs.

Findings

IMCs have an upper bound on SNR due to energy, area, and voltage constraints.

MPC enables near-ideal SNR with minimal ADC precision.

QS-based architectures are optimal for low SNR, QR-based for high SNR scenarios.

Abstract

This paper obtains fundamental limits on the computational precision of in-memory computing architectures (IMCs). An IMC noise model and associated SNR metrics are defined and their interrelationships analyzed to show that the accuracy of IMCs is fundamentally limited by the compute SNR ($\text{SNR}_{\text{a}}$) of its analog core, and that activation, weight and output precision needs to be assigned appropriately for the final output SNR $\text{SNR}_{\text{T}} \rightarrow \text{SNR}_{\text{a}}$. The minimum precision criterion (MPC) is proposed to minimize the ADC precision. Three in-memory compute models - charge summing (QS), current summing (IS) and charge redistribution (QR) - are shown to underlie most known IMCs. Noise, energy and delay expressions for the compute models are developed and employed to derive expressions for the SNR, ADC precision, energy, and latency of IMCs. The compute SNR expressions are validated via Monte Carlo simulations in a 65 nm CMOS process. For a 512 row SRAM array, it is shown that: 1) IMCs have an upper bound on their maximum achievable $\text{SNR}_{\text{a}}$ due to constraints on energy, area and voltage swing, and this upper bound reduces with technology scaling for QS-based architectures; 2) MPC enables $\text{SNR}_{\text{T}} \rightarrow \text{SNR}_{\text{a}}$ to be realized with minimal ADC precision; 3) QS-based (QR-based) architectures are preferred for low (high) compute SNR scenarios.