Design Rule Checking with a CNN Based Feature Extractor

TL;DR

This paper proposes a CNN-based model for fast, accurate design rule checking in integrated circuit layouts, demonstrating significant speed improvements over traditional methods for metal 1 rules.

Contribution

It introduces a CNN-based approach trained on artificial data to efficiently detect DRC violations, showing potential for real-time layout verification.

Findings

32x faster detection than Boolean checkers

up to 92% accuracy in violation detection

demonstrated on metal 1 rules from SRAM designs

Abstract

Design rule checking (DRC) is getting increasingly complex in advanced nodes technologies. It would be highly desirable to have a fast interactive DRC engine that could be used during layout. In this work, we establish the proof of feasibility for such an engine. The proposed model consists of a convolutional neural network (CNN) trained to detect DRC violations. The model was trained with artificial data that was derived from a set of $50$ SRAM designs. The focus in this demonstration was metal 1 rules. Using this solution, we can detect multiple DRC violations 32x faster than Boolean checkers with an accuracy of up to 92. The proposed solution can be easily expanded to a complete rule set.