A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching,

TL;DR

This paper presents a fully pipelined FPGA hardware accelerator for SIFT keypoint descriptor matching, significantly reducing resource usage and increasing speed compared to software implementations.

Contribution

The work introduces a novel fully pipelined FPGA architecture for SIFT matching that optimizes resource use and achieves maximum throughput, outperforming existing solutions.

Findings

Up to 91% reduction in LUTs resource usage

Up to 79% reduction in BRAMs resource usage

15.7 times faster than software implementation

Abstract

The scale invariant feature transform (SIFT) algorithm is considered a classical feature extraction algorithm within the field of computer vision. SIFT keypoint descriptor matching is a computationally intensive process due to the amount of data consumed. In this work, we designed a novel fully pipelined hardware accelerator architecture for SIFT keypoint descriptor matching. The accelerator core was implemented and tested on a field programmable gate array (FPGA). The proposed hardware architecture is able to properly handle the memory bandwidth necessary for a fully-pipelined implementation and hits the roofline performance model, achieving the potential maximum throughput. The fully pipelined matching architecture was designed based on the consine angle distance method. Our architecture was optimized for 16-bit fixed-point operations and implemented on hardware using a Xilinx Zynq-based FPGA development board. Our proposed architecture shows a noticeable reduction of area resources compared with its counterparts in literature, while maintaining high throughput by alleviating memory bandwidth restrictions. The results show a reduction in consumed device resources of up to 91 percent in LUTs and 79 percent of BRAMs. Our hardware implementation is 15.7 times faster than the comparable software approach.