Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers

TL;DR

This paper explores using machine learning on source code features to predict optimal energy configurations in ultra-low-power, parallel RISC-V microcontrollers, aiming to automate energy-efficient system setup.

Contribution

It demonstrates that static compile-time source code features can effectively predict the best energy scaling configuration for PULP architectures, a novel approach in this domain.

Findings

Machine learning models can predict energy-efficient configurations.

Static code features are sufficient for accurate predictions.

Potential for automating energy minimization in embedded systems.

Abstract

The analysis of source code through machine learning techniques is an increasingly explored research topic aiming at increasing smartness in the software toolchain to exploit modern architectures in the best possible way. In the case of low-power, parallel embedded architectures, this means finding the configuration, for instance in terms of the number of cores, leading to minimum energy consumption. Depending on the kernel to be executed, the energy optimal scaling configuration is not trivial. While recent work has focused on general-purpose systems to learn and predict the best execution target in terms of the execution time of a snippet of code or kernel (e.g. offload OpenCL kernel on multicore CPU or GPU), in this work we focus on static compile-time features to assess if they can be successfully used to predict the minimum energy configuration on PULP, an ultra-low-power architecture featuring an on-chip cluster of RISC-V processors. Experiments show that using machine learning models on the source code to select the best energy scaling configuration automatically is viable and has the potential to be used in the context of automatic system configuration for energy minimisation.