BinArray: A Scalable Hardware Accelerator for Binary Approximated CNNs

TL;DR

BinArray is a scalable FPGA-based hardware accelerator for binary-approximated CNNs that reduces computational costs and allows dynamic trade-offs between accuracy and throughput, enabling efficient real-time inference on low-power devices.

Contribution

This paper introduces BinArray, a novel hardware accelerator for binary CNNs that offers scalable performance and dynamic accuracy-throughput trade-offs, optimized for FPGA implementation.

Findings

Operates at 400 MHz on FPGA-SoC platform.

Scales to match performance of EdgeTPU for various networks.

Uses only 50% of device resources for MobileNet inference.

Abstract

Deep Convolutional Neural Networks (CNNs) have become state-of-the art for computer vision and other signal processing tasks due to their superior accuracy. In recent years, large efforts have been made to reduce the computational costs of CNNs in order to achieve real-time operation on low-power embedded devices. Towards this goal we present BinArray, a custom hardware accelerator for CNNs with binary approximated weights. The binary approximation used in this paper is an improved version of a network compression technique initially suggested in [1]. It drastically reduces the number of multiplications required per inference with no or very little accuracy degradation. BinArray easily scales and allows to compromise between hardware resource usage and throughput by means of three design parameters transparent to the user. Furthermore, it is possible to select between high accuracy or throughput dynamically during runtime. BinArray has been optimized at the register transfer level and operates at 400 MHz as instruction-set processor within a heterogenous XC7Z045-2 FPGA-SoC platform. Experimental results show that BinArray scales to match the performance of other accelerators like EdgeTPU [2] for different network sizes. Even for the largest MobileNet only 50% of the target device and only 96 DSP blocks are utilized.