Low-Latency Asynchronous Logic Design for Inference at the Edge

TL;DR

This paper introduces a low-latency, energy-efficient asynchronous inference circuit for edge IoT devices, leveraging learning automata principles to enhance robustness and reduce latency by tenfold compared to traditional synchronous designs.

Contribution

It presents a novel self-timed asynchronous inference circuit based on learning automata, achieving significant latency reduction and robustness for edge machine learning applications.

Findings

Latency reduced by 10x compared to synchronous circuits

Maintains similar area despite lower latency

Proven robustness across a wide voltage range

Abstract

Modern internet of things (IoT) devices leverage machine learning inference using sensed data on-device rather than offloading them to the cloud. Commonly known as inference at-the-edge, this gives many benefits to the users, including personalization and security. However, such applications demand high energy efficiency and robustness. In this paper we propose a method for reduced area and power overhead of self-timed early-propagative asynchronous inference circuits, designed using the principles of learning automata. Due to natural resilience to timing as well as logic underpinning, the circuits are tolerant to variations in environment and supply voltage whilst enabling the lowest possible latency. Our method is exemplified through an inference datapath for a low power machine learning application. The circuit builds on the Tsetlin machine algorithm further enhancing its energy efficiency. Average latency of the proposed circuit is reduced by 10x compared with the synchronous implementation whilst maintaining similar area. Robustness of the proposed circuit is proven through post-synthesis simulation with 0.25 V to 1.2 V supply. Functional correctness is maintained and latency scales with gate delay as voltage is decreased.