A Single-Cycle MLP Classifier Using Analog MRAM-based Neurons and Synapses

TL;DR

This paper introduces a novel analog IMC architecture using SOT-MRAM devices for neurons and synapses, achieving significant power and area efficiency improvements in neural network classification tasks.

Contribution

It proposes a new SOT-MRAM-based neuron and synapse design and integrates them into an analog IMC architecture for efficient neural network computation.

Findings

12x reduction in power-area-product for neuron bitcell

Achieves 2-4 orders of magnitude performance improvement over digital and mixed-signal architectures

Maintains comparable classification accuracy on MNIST

Abstract

In this paper, spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) devices are leveraged to realize sigmoidal neurons and binarized synapses for a single-cycle analog in-memory computing (IMC) architecture. First, an analog SOT-MRAM-based neuron bitcell is proposed which achieves a 12x reduction in power-area-product compared to the previous most power- and area-efficient analog sigmoidal neuron design. Next, proposed neuron and synapse bit cells are used within memory subarrays to form an analog IMC-based multilayer perceptron (MLP) architecture for the MNIST pattern recognition application. The architecture-level results exhibit that our analog IMC architecture achieves at least two and four orders of magnitude performance improvement compared to a mixed-signal analog/digital IMC architecture and a digital GPU implementation, respectively while realizing a comparable classification accuracy.