Physical Mechanism behind the Hysteresis-free Negative Capacitance Effect in Metal-Ferroelectric-Insulator-Metal Capacitors with Dielectric Leakage and Interfacial Trapped Charges
Chia-Sheng Hsu, Sou-Chi Chang, Dmitri E. Nikonov, Ian A. Young, and, Azad Naeemi

TL;DR
This paper explains the physical mechanisms behind hysteresis-free negative capacitance in metal-ferroelectric-insulator-metal capacitors, highlighting the roles of dielectric leakage and interfacial trapped charges in charge enhancement.
Contribution
It introduces a physical model incorporating dielectric leakage and trapped charges to explain hysteresis-free negative capacitance phenomena in MFIM capacitors, supported by simulations and experimental data.
Findings
Hysteresis-free charge boost is dominated by ferroelectric domain viscosity.
Dielectric leakage influences hysteresis behavior.
Interfacial trapped charges contribute to residual charge dynamics.
Abstract
The negative capacitance (NC) stabilization of a ferroelectric (FE) material can potentially provide an alternative way to further reduce the power consumption in ultra-scaled devices and thus has been of great interest in technology and science in the past decade. In this article, we present a physical picture for a better understanding of the hysteresis-free charge boost effect observed experimentally in metal-ferroelectric-insulator-metal (MFIM) capacitors. By introducing the dielectric (DE) leakage and interfacial trapped charges, our simulations of the hysteresis loops are in a strong agreement with the experimental measurements, suggesting the existence of an interfacial oxide layer at the FE-metal interface in metal-ferroelectric-metal (MFM) capacitors. Based on the pulse switching measurements, we find that the charge enhancement and hysteresis are dominated by the FE domain…
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