Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications

TL;DR

This paper proposes a novel 3D high-density in-memory computing architecture using stacked junctionless nanowires combined with OxRAM technology, addressing area efficiency and enabling multi-layer logic operations.

Contribution

It introduces a new 3D memory pillar design with stacked junctionless nanowires and OxRAM, enhancing density while maintaining control, and demonstrates multi-layer logic operations through simulations.

Findings

Successful fabrication and characterization of junctionless nanowires.

SPICE simulations show multi-layer logic operations up to three pillars.

The proposed design significantly increases memory density for in-memory computing.

Abstract

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.