Laser Processing For 3D Junctionless Transistor Fabrication

TL;DR

This paper explores a laser-assisted process at 475°C for fabricating 13nm junctionless transistors with smooth poly-silicon layers, optimizing grain size through nanosecond laser annealing to enhance device quality.

Contribution

It introduces a low-temperature laser processing method for fabricating ultra-thin junctionless transistors with optimized grain size and surface roughness.

Findings

Achieved a 13nm doped poly-silicon film with excellent surface roughness.

Provided guidelines for grain size optimization using nanosecond laser annealing.

Demonstrated a low-cost, low-temperature fabrication process for junctionless transistors.

Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.