Design Methodologies for Reliable and Energy-efficient PCM Systems

TL;DR

This paper proposes methodologies to enhance the performance, reliability, and energy efficiency of phase-change memory systems by addressing key bottlenecks related to write latency, energy consumption, and high operating voltages.

Contribution

It introduces novel design methodologies specifically targeting the reduction of write latency and energy use, and improving reliability in PCM systems.

Findings

Reduced write latency and energy consumption in PCM systems.

Improved reliability under high operating voltages.

Enhanced sustainability of PCM technology.

Abstract

Phase-change memory (PCM) is a scalable and low latency non-volatile memory (NVM) technology that has been proposed to serve as storage class memory (SCM), providing low access latency similar to DRAM and often approaching or exceeding the capacity of SSD. The multilevel property of PCM also enables its adoption in neuromorphic systems to build high-density synaptic storage. We investigate and describe two significant bottlenecks of a PCM system. First, writing to PCM cells incurs significantly higher latency and energy penalties than reading its content. Second, high operating voltages of PCM impacts its reliable operations. In this work, we propose methodologies to tackle the bottlenecks, improving performance, reliability, energy consumption, and sustainability for a PCM system.