On-Chip Error-triggered Learning of Multi-layer Memristive Spiking Neural Networks

TL;DR

This paper introduces a novel on-chip, error-triggered learning algorithm for multi-layer spiking neural networks using memristive hardware, enabling online training with low power consumption and minimal performance loss.

Contribution

It presents a new local, gradient-based learning algorithm with online ternary weight updates and a memristive crossbar architecture for efficient in situ training of SNNs.

Findings

Achieved online training of multi-layer SNNs with minimal performance loss.

Designed power-efficient peripheral circuitry in 180 nm CMOS.

Demonstrated feasibility of memristive hardware for gradient-based learning.

Abstract

Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradient-descent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multi-layer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared with the state of the art. We also propose a hardware architecture based on memristive crossbar arrays to perform the required vector-matrix multiplications. The necessary peripheral circuitry including pre-synaptic, post-synaptic and write circuits required for online training, have been designed in the sub-threshold regime for power saving with a standard 180 nm CMOS process.