Linearization for High-Speed Current-Steering DACs Using Neural Networks

TL;DR

This paper introduces a neural network-based linearization method for high-speed current-steering DACs, significantly enhancing intermodulation performance at multi-gigahertz frequencies in advanced CMOS technology.

Contribution

It presents a novel foreground linearization scheme using neural networks to improve high-speed DAC linearity beyond conventional techniques.

Findings

At least 6dB IM performance improvement

Effective up to 9GHz frequency

Applicable to 10-bit 40.96GS/s CS-DAC in 14nm CMOS

Abstract

This paper proposes a novel foreground linearization scheme for a high-speed CS-DAC. The technique leverages neural networks (NNs) to derive a LUT that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm is shown to improve conventional methods by at least 6dB in terms of intermodulation (IM) performance for frequencies up to 9GHz on a state-of-the-art 10-bit CS-DAC operating at 40.96GS/s (gigasamples-per-second) in 14nm CMOS.