Hardware Implementation of Fano Decoder for Polarization-adjusted Convolutional (PAC) Codes

TL;DR

This paper presents a hardware architecture for Fano decoding of PAC codes, demonstrating high-speed FPGA implementation and ASIC performance evaluation with significant throughput at practical SNR levels.

Contribution

It introduces a novel branch metric unit tailored for PAC codes and implements a high-speed Fano decoder on FPGA and ASIC platforms.

Findings

Decoder operates at 500 MHz on FPGA

Achieves 38 Mb/s throughput at 3.5 dB SNR

Demonstrates effective hardware implementation for PAC codes

Abstract

This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2.