Automatic test system of the back-end card for the JUNO experiment

TL;DR

This paper presents an automated FPGA-based testing system for verifying the physical link performance of back-end cards in the JUNO neutrino experiment, ensuring reliable communication between underwater electronics and the trigger system.

Contribution

The paper introduces a custom FPGA-based automatic test system utilizing JTAG for efficient, simultaneous testing of multiple channels in JUNO's back-end electronics.

Findings

Successfully tested 1024 clock cycles across 96 channels

Automated data pattern generation and checking at various speeds

Periodic upload of test results to PC for analysis

Abstract

The Jiangmen Underground Neutrino Observatory (JUNO) is a medium-baseline neutrino experiment under construction in China, with the goal to determine the neutrino mass hierarchy. The JUNO electronics readout system consists of an underwater front-end electronics system and an outside-water back-end electronics system. These two parts are connected by 100-meter Ethernet cables and power cables. The back-end card (BEC) is the part of the JUNO electronics readout system used to link the underwater boxes to the trigger system is connected to transmit the system clock and triggered signals. Each BEC is connected to 48 underwater boxes, and in total around 150 BECs are needed. It is essential to verify the physical layer links before applying real connection with the underwater system. Therefore, our goal is to build an automatic test system to check the physical link performance. The test system is based on a custom designed FPGA board, in order to make the design general, only JTAG is used as the interface to the PC. The system can generate and check different data pattern at different speeds for 96 channels simultaneously. The test results of 1024 continuously clock cycles are automatically uploaded to PC periodically. We describe the setup of the automatic test system of the BEC and present the latest test results.