Hardware Complexity Aware Design Strategy for a Fused Logarithmic and Anti-Logarithmic Converter

TL;DR

This paper presents a hardware-efficient design strategy for a fused logarithmic and anti-logarithmic converter using shared components and formulas to optimize area and latency in shift-and-add architectures.

Contribution

It introduces a shared architecture for Log and Antilog converters, reducing hardware cost, and provides formulas to predict area and latency for optimized design trade-offs.

Findings

Shared adder tree reduces hardware complexity.

Fused converter achieves 14% area increase with 6% latency increase.

Formulas enable efficient trade-off analysis in design space.

Abstract

The logarithmic and anti-logarithmic converters are realized with the piecewise linear approximation method, which is implemented by the shift-and-add architecture. This brief utilizes the similarities of Log and Antilog functions so that the adder tree block and multiplexer block can be shared by the Log and Antilog converters. As a result, the Antilog function can be implemented by the Log converter at the cost of additional 14% area and 6% latency. It implies the shift-and-add architecture can approximate multiple similar nonlinear functions with a slightly hardware cost. In addition, this brief proposes a set of formulas to predict the area and latency of shift-and-add architecture with different quantized coefficients that can facilitate the finding of a trade-off point in the Latency-Area-Precision space.