Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits

TL;DR

This paper presents a new multi-layer fabrication process for large-scale superconducting digital circuits using Nb-based Josephson junctions, emphasizing process optimization and film quality control.

Contribution

It introduces a systematic fabrication process with 10 mask levels and detailed control of film properties for scalable superconducting circuits.

Findings

Successful deposition of high-quality Nb, Al, Mo, and SiO2 films.

Development of process control methods for film thickness and etch depth.

Achievement of target electrical properties for circuit components.

Abstract

We have developed a fabrication technology for the development of large-scale superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels uses four metal layers including 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2 films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 2 Ome, followed by the deposition of Josephson-junction. The target critical current density Jc was set at 6 kA per cm2. The thicknesses and etch depths of the films were monitored during fabrication with on-wafer process-control-monitor (PCM) patterns for all the wafers.