Coherence Traffic in Manycore Processors with Opaque Distributed Directories

TL;DR

This paper analyzes the coherence traffic in manycore processors with distributed directories, revealing the pseudo-random mapping of memory blocks and exploring optimizations to reduce latency, which improve throughput but not overall performance.

Contribution

It uncovers the pseudo-random memory mapping in Intel Knights Landing processors and evaluates optimizations to reduce coherence traffic and memory latency.

Findings

Optimizations reduce coherence traffic and improve memory throughput.

Memory latency improvements do not translate into overall performance gains.

The memory block mapping function is pseudo-random and complex.

Abstract

Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh interconnect, which consists of a network-on-chip interconnecting "tiles", each of which contains computation cores, local caches, and coherence masters. The distributed coherence subsystem must be queried for every out-of-tile access, imposing an overhead on memory latency. This paper studies the physical layout of an Intel Knights Landing processor, with a particular focus on the coherence subsystem, and uncovers the pseudo-random mapping function of physical memory blocks across the pieces of the distributed directory. Leveraging this knowledge, candidate optimizations to improve memory latency through the minimization of coherence traffic are studied. Although these optimizations do improve memory throughput, ultimately this does not translate into performance gains due to inherent overheads stemming from the computational complexity of the mapping functions.