Remote Configuration of the ProASIC3 on the ALICE Inner Tracking System Readout Unit

TL;DR

This paper describes the development of remote configuration tools for the Microsemi ProASIC3 FPGA used in CERN's ALICE experiment to ensure continuous operation and upgrade capability in a radiation environment.

Contribution

It introduces a novel distributed software system enabling remote reconfiguration of ProASIC3 FPGAs in a high-radiation physics experiment setting.

Findings

Successful implementation of remote FPGA reconfiguration tools

Enhanced system reliability during data acquisition

Facilitated FPGA upgrades without physical access

Abstract

A Large Ion Collider Experiment (ALICE) is one of the four major experiments conducted at the CERN Large Hadron Collider (LHC). The ALICE detector is currently undergoing an upgrade for the upcoming Run 3 at the LHC. The new Inner Tracking System (ITS) sub-detector is part of this upgrade. The front-end electronics of the ITS is composed by 192 Readout Units, installed in a radiation environment. Single Event Upsets (SEUs) in the SRAM-based Xilinx Kintex Ultrascale FPGAs used in the ITS readout represent a real concern. To clear SEUs affecting the Kintex configuration memory, a secondary Flash-based Microsemi ProASIC3E (PA3) FPGA is used. This device configures and continuously scrubs the Xilinx FPGA while data-taking is ongoing, which avoids accumulation of SEUs. The communication path to the RUs is via the radiation hard Gigabit Transceiver (GBT) system on 100 m long optical links. The PA3 is reachable via the GBT Slow Control Adapter (GBT-SCA) ASIC using a dedicated JTAG bus driving channel. During the course of Run 3, it is foreseeable that the FPGA design of the PA3 will require upgrades to correct possible issues and add new functionality. It is therefore mandatory that the PA3 itself can be configured remotely, for which a dedicated software tool is needed. This paper presents the design and implementation of the distributed tools to re-configure remotely the PA3 FPGAs.