Dimensional Expressivity Analysis of Parametric Quantum Circuits

TL;DR

This paper introduces a method to analyze and optimize the expressivity of parametric quantum circuits, enabling the design of efficient, minimally parameterized ansatzes for variational quantum algorithms using hybrid quantum-classical techniques.

Contribution

We develop a novel approach to assess and enhance the expressivity of parametric quantum circuits, including symmetry considerations and hardware implementation, to improve variational algorithm performance.

Findings

Efficient identification of superfluous parameters in quantum circuits.

Demonstration of expressivity analysis on IBM quantum hardware.

Insights into symmetry effects on circuit expressivity.

Abstract

Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, we develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.