Testing of flag-based fault-tolerance on IBM quantum devices

TL;DR

This paper introduces a benchmarking method to test flag-based fault-tolerant quantum error correction on NISQ devices, demonstrating its feasibility using IBM's quantum hardware and simulator.

Contribution

It proposes a practical testing approach for fault-tolerant quantum error correction with flags on current quantum devices, bridging the gap between NISQ and FTQC.

Findings

Flagged scheme is testable on NISQ devices.

Overlap with expected state indicates fault-tolerance performance.

Method validated on IBM's 15-qubit Melbourne processor.

Abstract

It is hard to achieve a theoretical quantum advantage on NISQ devices. Besides the attempts to reduce error using error mitigation and dynamical decoupling, small quantum error correction and fault-tolerant schemes that reduce the high overhead of traditional schemes have also been proposed. According to the recent advancements in fault tolerance, it is possible to minimize the number of ancillary qubits using flags. While implementing those schemes is still impossible, it is worthwhile to bridge the gap between the NISQ era and the FTQC era. Here, we introduce a benchmarking method to test fault-tolerant quantum error correction with flags for the [[5,1,3]] code on NISQ devices. Based on results obtained using IBM's qasm simulator and its 15-qubit Melbourne processor, we show that this flagged scheme is testable on NISQ devices by checking how much the subspace of intermediate state overlaps with the expected state in the presence of noise.