An SMT-Based Approach for Verifying Binarized Neural Networks

TL;DR

This paper introduces an SMT-based method for verifying Binarized Neural Networks, including mixed architectures, with optimizations and parallelization, implemented in Marabou and tested on popular models.

Contribution

It presents a novel SMT-based verification technique for mixed binarized and non-binarized neural networks, with optimizations and parallelization, extending the Marabou framework.

Findings

Effective verification of mixed neural networks demonstrated

Optimizations improve verification efficiency

Parallelization accelerates the verification process

Abstract

Deep learning has emerged as an effective approach for creating modern software systems, with neural networks often surpassing hand-crafted systems. Unfortunately, neural networks are known to suffer from various safety and security issues. Formal verification is a promising avenue for tackling this difficulty, by formally certifying that networks are correct. We propose an SMT-based technique for verifying Binarized Neural Networks - a popular kind of neural network, where some weights have been binarized in order to render the neural network more memory and energy efficient, and quicker to evaluate. One novelty of our technique is that it allows the verification of neural networks that include both binarized and non-binarized components. Neural network verification is computationally very difficult, and so we propose here various optimizations, integrated into our SMT procedure as deduction steps, as well as an approach for parallelizing verification queries. We implement our technique as an extension to the Marabou framework, and use it to evaluate the approach on popular binarized neural network architectures.