A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade
Wei Zhang (1,2), Hanhan Sun (1,2), Christopher Edwards (3), Datao Gong, (1), Xing Huang (1,2), Chonghan Liu (1), Tiankuan Liu (1), Tiehui Liu (3),, Jamieson Olsen (3), Quan Sun (3), Xiangming Sun (2), Jinyuan Wu (3), Jingbo, Ye (1), Li Zhang (1

TL;DR
This paper introduces a low-power, high-precision Time-to-Digital Converter (TDC) designed for the CMS Endcap Timing Layer upgrade, achieving sub-20 ps resolution with minimal power consumption in a 65 nm CMOS process.
Contribution
It presents a novel low-power TDC design with self-calibration and a single delay line, optimized for high-luminosity collider environments and integrated into the ETROC ASIC.
Findings
Achieved 17.8 ps bin size for TOA measurement.
Consumed only 97 W at 1% hit occupancy.
Maintained stable performance across temperature and voltage variations.
Abstract
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65 nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective…
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