A $0.11-0.38$ pJ/cycle Differential Ring Oscillator in $65$ nm CMOS for Robust Neurocomputing

TL;DR

This paper introduces a low-power, low-area differential current controlled oscillator in 65 nm CMOS technology, optimized for neuromorphic systems, achieving high frequency and energy efficiency with minimal nonlinearity impact.

Contribution

It presents a novel CMOS CCO design with reduced transistor count and load capacitor, improving frequency and power efficiency for neuromorphic applications.

Findings

Oscillator operates from 0.7-1.2 V with up to 80 MHz frequency.

Energy per cycle ranges from 0.11 to 0.38 pJ.

Nonlinearity does not significantly affect neural network performance.

Abstract

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about $11\%$ compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced $15\%$ at the same frequency. The prototype structures are fabricated in a standard $65$ nm CMOS technology and measurements demonstrate that the proposed CCO operates from $0.7-1.2$ V supply with maximum frequencies of $80$ MHz and energy/cycle ranging from $0.11-0.38$ pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.