Addressing Resiliency of In-Memory Floating Point Computation
Sina Sayyah Ensan, Swaroop Ghosh, Seyedhamidreza Motaman, and Derek, Weast

TL;DR
This paper introduces FAME, a pipelined floating point adder using RRAM-based in-memory computing, with novel fault mitigation techniques that significantly improve fault tolerance at low power and area costs.
Contribution
It proposes a new RRAM-based FP adder architecture with innovative shift circuitry and fault mitigation methods, enhancing resiliency and efficiency in in-memory computing.
Findings
FAME achieves low energy consumption of around 330 pJ per operation.
SATO and FTV techniques handle up to 50% and 99% of RRAM faults respectively.
The architecture incurs modest area overheads of 28.5% and 9.5%.
Abstract
In-memory computing (IMC) can eliminate the data movement between processor and memory which is a barrier to the energy-efficiency and performance in Von-Neumann computing. Resistive RAM (RRAM) is one of the promising devices for IMC applications (e.g. integer and Floating Point (FP) operations and random logic implementation) due to low power consumption, fast operation, and small footprint in crossbar architecture. In this paper, we propose FAME, a pipelined FP arithmetic (adder/subtractor) using RRAM crossbar based IMC. A novel shift circuitry is proposed to lower the shift overhead during FP operations. Since 96% of the RRAMs used in our architecture are in High Resistance State (HRS), we propose two approaches namely Shift-At-The-Output (SATO) and Force To VDD (FTV) (ground (FTG)) to mitigate Stuck-at-1 (SA1) failures. In both techniques, the fault-free RRAMs are exploited to…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Advanced Data Storage Technologies
