A Non-Volatile Cryogenic Random-Access Memory Based on the Quantum Anomalous Hall Effect

TL;DR

This paper presents a cryogenic, non-volatile memory device utilizing the quantum anomalous Hall effect in moiré graphene, achieving ultra-low power operation, high density, and topological protection for future electronics.

Contribution

It introduces a novel memory architecture based on QAHE, demonstrating non-volatile binary storage with controlled hysteretic switching and a new sensing mechanism to prevent data corruption.

Findings

Achieves orders of magnitude smaller cell area than existing cryogenic memories.

Demonstrates reliable write and read operations using quantized Hall resistance levels.

Provides a scalable, material-agnostic platform for topologically protected memory devices.

Abstract

The interplay between ferromagnetism and topological properties of electronic band structures leads to a precise quantization of Hall resistance without any external magnetic field. This so-called quantum anomalous Hall effect (QAHE) is born out of topological correlations, and is oblivious of low-sample quality. It was envisioned to lead towards dissipationless and topologically protected electronics. However, no clear framework of how to design such an electronic device out of it exists. Here we construct an ultra-low power, non-volatile, cryogenic memory architecture leveraging the QAHE phenomenon. Our design promises orders of magnitude lower cell area compared with the state-of-the-art cryogenic memory technologies. We harness the fundamentally quantized Hall resistance levels in moir\'e graphene heterostructures to store non-volatile binary bits (1, 0). We perform the memory write operation through controlled hysteretic switching between the quantized Hall states, using nano-ampere level currents with opposite polarities. The non-destructive read operation is performed by sensing the polarity of the transverse Hall voltage using a separate pair of terminals. We custom design the memory architecture with a novel sensing mechanism to avoid accidental data corruption, ensure highest memory density and minimize array leakage power. Our design is transferrable to any material platform exhibiting QAHE, and provides a pathway towards realizing topologically protected memory devices.