Multi-Core Processor Scheduling with Respect to Data Bus Bandwidth

TL;DR

This paper addresses the challenge of scheduling software modules on multi-core processors considering data bus bandwidth limitations and precedence constraints, proposing models and algorithms to optimize performance.

Contribution

It introduces two problem formulations with different detail levels, proves their NP-hardness, and develops a MILP model and a greedy algorithm for scheduling.

Findings

The MILP model provides optimal solutions for small instances.

The greedy algorithm offers a scalable heuristic approach.

Experimental results compare the effectiveness of both methods.

Abstract

The paper considers the problem of scheduling software modules on a multi-core processor, taking into account the limited bandwidth of the data bus and the precedence constraints. Two problem formulations with different levels of problem-specific detail are suggested and both shown to be NP-hard. A mixed integer linear programming (MILP) model is proposed for the first problem formulation, and a greedy algorithm is developed for the second one. An experimental comparison of the results of the greedy algorithm and the MILP solutions found by CPLEX solver is carried out.