FPGA Implementation of Stair Matrix based Massive MIMO Detection

TL;DR

This paper presents an FPGA implementation of a stair matrix based iterative detector for massive MIMO systems, achieving high data rates and improved error-rate performance compared to existing methods.

Contribution

It introduces a novel VLSI architecture and FPGA implementation of a stair matrix based detector for large-scale MIMO, enhancing performance and throughput.

Findings

Achieves 142.34 Mbps data rate at 258 MHz clock frequency.

Supports 128 antennas, 8 users, 256-QAM modulation.

Provides superior error-rate performance and throughput.

Abstract

Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex-7 FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.