PCI-express based high-speed readout for the BelleII DAQ upgrade

TL;DR

This paper presents a high-speed PCIe-based readout system upgrade for the Belle II experiment's DAQ, significantly improving data throughput and maintainability with a novel firmware and hardware design.

Contribution

The paper introduces a PCIe40 readout module with high data throughput, integrating advanced firmware and hardware to enhance Belle II DAQ system performance and maintainability.

Findings

Achieved data readout speeds up to 100 Gb/s.

Successfully integrated with Belle II sub-detectors in tests.

Demonstrated reliable performance in on-site tests.

Abstract

Belle II is a new-generation B-factory experiment, dedicated to exploring new physics beyond the standard model of elementary particles in the flavor sector. Belle~II started data-taking in April 2018, using a synchronous data acquisition (DAQ) system based on pipelined trigger flow control. The Belle II DAQ system is designed to handle a 30-kHz trigger rate with approximately 1% of dead time, under the assumption of a raw event size of 1 MB. The DAQ system is reliable, and the overall data-taking efficiency reached 84.2% during the run period of January 2020 to June 2020. The current readout system cannot be operated in the term of 10 years from the viewpoint of DAQ maintainability; meanwhile, the readout system is obstructing high-speed data transmission. A solution involving a PCI-express-based readout module with high data throughput of up to 100 Gb/s was adopted to upgrade the Belle II DAQ system. We particularly focused on the design of firmware and software based on this new generation of readout board, called PCIe40, with an Altera Arria 10 field-programmable gate array chip. Forty-eight GBT (GigaBit Transceiver) serial links, PCI-express hard IP-based DMA architecture, interface of timing and trigger distribution system, and slow control system were designed to integrate with the current Belle II DAQ system. This paper describes the performances accomplished during the data readout and slow control tests conducted using a test bench and a demonstration performed using on-site front-end electronics, specifically involving Belle II TOP and KLM sub-detectors.