New software based readout driver for the ATLAS experiment

TL;DR

The paper introduces a new software-based readout driver for the ATLAS experiment, replacing legacy hardware to improve data processing under harsher conditions, with high-performance capabilities demonstrated in tests.

Contribution

It presents the design and implementation of a highly customizable, high-performance software readout driver for the ATLAS experiment's data acquisition system.

Findings

Supports event building at 100 kHz rate

Handles up to 120 MHz data packets

Demonstrates performance on selected server models

Abstract

In order to maintain sensitivity to new physics in the coming years of LHC operations, the ATLAS experiment has been working on upgrading a portion of the front-end electronics and replacing some parts of the detector with new devices that can operate under the much harsher background conditions of the future LHC. The legacy front-end of the ATLAS detector sent data to the DAQ system via so called Read Out Drivers (ROD) - custom made VMEbus boards devoted to data processing, configuration and control. The data were then received by the Read Out System (ROS), which was responsible for buffering them during High-Level Trigger (HLT) processing. From Run 3 onward, all new trigger and detector systems will be read out using new components, replacing the combination of the ROD and the ROS. This new path will feature an application called the Software Read Out Driver (SW ROD), which will run on a commodity server receiving front-end data via the Front-End Link eXchange (FELIX) system. The SW ROD will perform event fragment building and buffering as well as serving the data on request to the HLT. The SW ROD application has been designed as a highly customizable high-performance framework providing support for detector specific event building and data processing algorithms. The implementation that will be used for the Run 3 is capable of building event fragments at a rate of 100 kHz from an input stream consisting of up to 120 MHz of individual data packets. This document will cover the design and the implementation of the SW ROD application and will present the results of performance measurements performed on the server models selected to host SW ROD applications in Run 3.