TL;DR
This paper introduces a novel local learning rule and integrated circuits to implement Efficient Balanced Networks in low-power neuromorphic hardware, enabling high-precision, low-rate spiking neural computations suitable for edge applications.
Contribution
The paper presents a new local learning rule and circuit design that facilitate the implementation of balanced spiking networks on analog neuromorphic hardware despite device mismatch.
Findings
Demonstrated the behavior of the circuits in low-level simulations.
Proposed a method for on-chip training of balanced networks.
Enabled potential for ultra-low power, high-precision neuromorphic computing.
Abstract
Efficient Balanced Networks (EBNs) are networks of spiking neurons in which excitatory and inhibitory synaptic currents are balanced on a short timescale, leading to desirable coding properties such as high encoding precision, low firing rates, and distributed information representation. It is for these benefits that it would be desirable to implement such networks in low-power neuromorphic processors. However, the degree of device mismatch in analog mixed-signal neuromorphic circuits renders the use of pre-trained EBNs challenging, if not impossible. To overcome this issue, we developed a novel local learning rule suitable for on-chip implementation that drives a randomly connected network of spiking neurons into a tightly balanced regime. Here we present the integrated circuits that implement this rule and demonstrate their expected behaviour in low-level circuit simulations. Our…
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