Clock-centric Serial Links for the Synchronization of Distributed Readout Systems
Denis Calvet

TL;DR
This paper introduces a novel clock-centric approach for distributing synchronized signals in distributed readout systems, potentially improving accuracy over traditional methods by embedding data into a dedicated clock signal.
Contribution
It proposes and explores a new scheme where clock signals are carried by the link itself, with data embedded via modulation, offering an alternative to existing data-centric and separate clock/data solutions.
Findings
Initial experimental validation of clock-centric links.
Comparison of clock-centric and traditional methods.
Discussion of advantages and limitations of the approach.
Abstract
Detector readout systems for medium to large scale physics experiments, and instruments in some other fields as well, are generally composed of multiple front-end digitizer boards distributed over a certain area. Often, this hardware has to be synchronized to a common reference clock with minimal skew and low jitter. Today's mainstream solutions to precise clock distribution and deterministic latency messaging rely on the capabilities of high speed serial transceivers (a.k.a. SerDes) embedded in modern Field Programmable Gate Arrays (FPGAs). An alternative option uses distinct clock and data links. This can potentially reach higher synchronization accuracy, at significant hardware expenses. This work reports some first steps to explore a third scheme for clock and synchronous message distribution. Like the standard approach, the same media is used to convey clock and data, but instead…
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