hXDP: Efficient Software Packet Processing on FPGA NICs
Marco Spaziani Brunella, Giacomo Belocchi, Marco Bonola, Salvatore, Pontarelli, Giuseppe Siracusano, Giuseppe Bianchi, Aniello Cammarano,, Alessandro Palumbo, Luca Petrucci, Roberto Bifulco

TL;DR
hXDP enables efficient, resource-light FPGA-based execution of Linux eBPF programs for packet processing, matching high-end CPU performance with significantly reduced latency.
Contribution
This work introduces hXDP, a novel FPGA-based framework that compiles and executes eBPF programs efficiently, overcoming FPGA resource constraints and programming complexity.
Findings
Achieves CPU-level packet processing throughput on FPGA.
Uses only 15% of FPGA resources for real-time eBPF execution.
Provides 10x lower packet forwarding latency.
Abstract
FPGA accelerators on the NIC enable the offloading of expensive packet processing tasks from the CPU. However, FPGAs have limited resources that may need to be shared among diverse applications, and programming them is difficult. We present a solution to run Linux's eXpress Data Path programs written in eBPF on FPGAs, using only a fraction of the available hardware resources while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized or completely removed, when targeting a purpose-built FPGA executor, thereby significantly improving performance. We leverage that to design hXDP, which includes (i) an optimizing-compiler that parallelizes and translates eBPF bytecode to an extended eBPF Instruction-set Architecture…
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Taxonomy
TopicsSoftware-Defined Networks and 5G · Interconnection Networks and Systems · Network Packet Processing and Optimization
