Track-Assignment Detailed Routing Using Attention-based Policy Model With Supervision

TL;DR

This paper introduces a supervised attention-based reinforcement learning method for track-assignment detailed routing in advanced node analog circuits, achieving near 100x faster solutions with comparable quality to genetic algorithms.

Contribution

It presents a novel supervised RL approach that leverages genetic algorithm solutions to significantly improve routing efficiency in analog circuit design.

Findings

Run-time improved nearly 100x over genetic algorithms

Solution quality matches traditional genetic algorithms

Effective for complex routing problems

Abstract

Detailed routing is one of the most critical steps in analog circuit design. Complete routing has become increasingly more challenging in advanced node analog circuits, making advances in efficient automatic routers ever more necessary. In this work, we propose a machine learning driven method for solving the track-assignment detailed routing problem for advanced node analog circuits. Our approach adopts an attention-based reinforcement learning (RL) policy model. Our main insight and advancement over this RL model is the use of supervision as a way to leverage solutions generated by a conventional genetic algorithm (GA). For this, our approach minimizes the Kullback-Leibler divergence loss between the output from the RL policy model and a solution distribution obtained from the genetic solver. The key advantage of this approach is that the router can learn a policy in an offline setting with supervision, while improving the run-time performance nearly 100x over the genetic solver. Moreover, the quality of the solutions our approach produces matches well with those generated by GA. We show that especially for complex problems, our supervised RL method provides good quality solution similar to conventional attention-based RL without comprising run time performance. The ability to learn from example designs and train the router to get similar solutions with orders of magnitude run-time improvement can impact the design flow dramatically, potentially enabling increased design exploration and routability-driven placement.