Exploring Memory Access Patterns for Graph Processing Accelerators

TL;DR

This paper presents a simulation environment to analyze and compare FPGA-based graph processing accelerators by focusing on their memory access patterns, aiming to improve development efficiency and benchmarking consistency.

Contribution

It introduces a simulation framework for analyzing memory access patterns in FPGA graph accelerators, enabling standardized benchmarking and easier development.

Findings

Simulation environment improves benchmarking consistency

Reduces development time for FPGA accelerators

Enables comparison of different graph processing approaches

Abstract

Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e.g., CPU). However, developing such hardware accelerators is yet time-consuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators. In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-of-the-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches.